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GS2985 multi-rate sdi reclocker with equalization & de-emphasis GS2985 1 of 45 proprietary & confidential GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 www.semtech.com features ? smpte 424m, smpte 292m and smpte 259m-c compliant ? supports dvb-asi at 270mb/s ? single supply operation at 3.3v or 2.5v ? 180mw typical power consumption (210mw with rco enabled) at 2.5v ? input signal equalization and output-signal de-emphasis settings to compensate for board-trace dielectric losses ? 4:1 input multiplexer patented technology ? choice of dual reclocked data outputs or one reclocked data output and one clock output ? uses standard 27mhz crystal ? cascadable crystal buffer supports multiple reclockers using a single crystal ? differential inputs and outputs ? support dc coupling to industry-standard differential logic ? on-chip 100 differential data input/output termination ? selectable 400mvppd or 800mvppd output swing on each output ? seamless interface to other gennum products ? 4 wire spi host interface for device configuration and monitoring ? standard logic control and status signal levels ? auto and manual modes for rate selection ? standards indication in auto mode ? lock detect output ? mute, bypass and autobypass functions ? sd/ hd indication output to control gs2978 or gs2988 dual slew-rate cable drivers ? operating temperature range: -40c to +85c ? small footprint qfn package (9mm x 9mm) ? package-compatible with gs2975a ? pb-free and rohs compliant applications ? smpte 424m, smpte 292m and smpte 259m-c coaxial cable serial digital interfaces description the GS2985 is a multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and retime the incoming video data. it will recover the embedded clock signal and retime the data from a smpte 424m, smpte 292m, or smpte 259m-c compliant digital video signal. a serial host interface provides the ability to configure and monitor multiple GS2985 devices in a daisy-chain configuration. adjustable input trace equalization (eq) for up to 40? of fr4 trace losses, and adjustable output de-emphasis (de) for up to 20? of fr4 trace losses, can be configured via the host interface. the GS2985 can operate in either auto or manual rate selection mode. in auto mode, the device will automatically detect and lock onto incoming smpte sdi data signals at any supported rate. for single rate data systems, the GS2985 can be configured to operate in manual mode. in both modes, the device requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. the GS2985 accepts industry-standard differential input levels including lvpecl and cml. the differential data and clock outputs feature selectable output swing via the host interface, ensuring compatibility with most industry-standard, terminated differential receivers. the GS2985 features dual differential outputs. the second output can be configured to emit either the recovered clock signal or the re-timed video data. this output can also be disabled to save power. in systems which require passing of non-smpte data rates, the GS2985 can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. the GS2985 is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous sub-components are rohs compliant.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 2 of 45 proprietary & confidential GS2985 functional block diagram revision history buffer control vco retimer spi ldo ldo xtal- cp_cap ddi0 ddi0 ddi1 ddi1 ddi2 ddi2 ddi3 ddi3 ddi_sel[1:0] los sdi/eq0_en sck/eq2_en sdo/eq1_en ddo0 de0_en ddo1/rco de1_en equalizer/ data mux xtal osc phase frequency detector phase detector selectable divide los detect charge pump selectable divide data buffer clock/ data buffer cs/eq3_en auto/man sd/hd data/clock data_mute ddo1_disable ddo0 ddo1/rco 1.8v xtal+ hif autobypass vdd_1p8 locked ss[1:0] bypass kbb lf+ xtal_buf_out version ecr pcn date changes and/or modifications 5 158296 ? july 2012 removed jumper from figure 5-1: GS2985 typical application circuit . 4 158127 ? may 2012 corrected 4.15.3 section to make it easier to follow and changed to semtech template. 3 158063 ? may 2012 corrected driver_1 [7:5] function description in table 4-12: host register map 2 153705 ? march 2010 converted to data sheet. updated power numbers in table 2-1: dc electrical characteristics . added table 4-5: suggested los threshold settings . 1 152592 ? september 2009 updates to section 4.15 host interface . 0 152329 ? july 2009 converted document to preliminary data sheet. d 152240 ? july 2009 added figure 4-2: de-emphasis waveform . c 152042 ? june 2009 removed ?proprietary & confidential? from document.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 3 of 45 proprietary & confidential b 151967 ? may 2009 added section 4.15 host interface . a 151318 ? april 2009 new document. version ecr pcn date changes and/or modifications
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 4 of 45 proprietary & confidential contents features....................................................................................................................... ..........................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 revision history ............................................................................................................... ..................................2 1. pin out..................................................................................................................... ..........................................5 1.1 pin assignment ............................................................................................................ ......................5 1.2 pin descriptions .......................................................................................................... ......................6 2. electrical characteristics .................................................................................................. ..........................9 2.1 absolute maximum ratings .................................................................................................. ........9 2.2 dc electrical characteristics ............................................................................................. ...........9 2.3 ac electrical characteristics ............................................................................................. ........ 10 3. input/output circuits ....................................................................................................... ........................ 13 4. detailed description........................................................................................................ .......................... 18 4.1 serial data input ......................................................................................................... ................... 18 4.2 modes of operation ........................................................................................................ .............. 18 4.3 input trace equalization .................................................................................................. ........... 18 4.4 4:1 input mux ............................................................................................................. ..................... 19 4.5 crystal buffer ............................................................................................................ ...................... 20 4.6 los (loss of signal) detection ............................................................................................ ...... 20 4.7 serial digital reclocker .................................................................................................. ............. 21 4.8 lock detection ............................................................................................................ .................... 21 4.8.1 lock detect and asynchronous lock ......................................................................... 22 4.9 serial data output ........................................................................................................ ................. 22 4.9.1 output signal interface levels...................................................................................... 22 4.9.2 adjustable output swing................................................................................................ 22 4.9.3 output de-emphasis ....................................................................................................... .22 4.10 automatic and manual data rate selection ...................................................................... 23 4.11 sd/ hd indication ................................................................................................................. ....... 24 4.12 bypass mode .............................................................................................................. ................... 25 4.13 dvb-asi .................................................................................................................. ....................... 25 4.14 output mute and data/clock output selection ............................................................... 25 4.15 host interface ........................................................................................................... .................... 26 4.15.1 introduction ............................................................................................................ .......... 26 4.15.2 legacy mode & start-up................................................................................................ 26 4.15.3 host interface mode & start-up.................................................................................. 26 4.15.4 clock & data timing..................................................................................................... .. 27 4.15.5 single device operation ............................................................................................... 27 4.15.6 write operation - single device ................................................................................ 28 4.15.7 read operation - single device ................................................................................. 28 4.15.8 daisy chain operation.................................................................................................. 3 1 4.15.9 read & write operation - daisy chained devices............................................... 32 4.15.10 writing to all devices ................................................................................................. .32
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 5 of 45 proprietary & confidential 4.15.11 writing to a single device in the chain ................................................................ 33 4.15.12 reading from all devices ........................................................................................... 33 4.15.13 reading from a single device in the chain.......................................................... 34 4.15.14 host register map...................................................................................................... ... 35 4.16 device power-up .......................................................................................................... ............... 39 4.17 standby .................................................................................................................. ......................... 39 5. typical application circuit ................................................................................................. .................... 40 6. package and ordering information............................................................................................ .......... 41 6.1 package dimensions ........................................................................................................ ............. 41 6.2 recommended pcb footprint ................................................................................................. .. 42 6.3 packaging data ............................................................................................................ ................... 42 6.4 marking diagram ........................................................................................................... ................ 43 6.5 solder reflow profile ..................................................................................................... ............... 43 6.6 ordering information ...................................................................................................... ............. 44
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 6 of 45 proprietary & confidential 1. pin out 1.1 pin assignment figure 1-1: GS2985 pin out 17 gnd 1 2 3 4 gnd gnd gnd 62 61 60 59 58 57 56 55 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 26 27 28 29 30 31 32 25 34 33 48 47 38 37 36 35 42 41 40 39 46 45 44 43 54 53 52 51 50 49 kbb 64 63 ddi0 hif ddi1 n/c ddi2 ddi3 rsvd ddi0 ddi1 ddi2 ddi3 ground pad (bottom of package) GS2985 64-pin qfn (top view) n/c xtal_buf_out xtal+ xtal- sck/eq2_en sdo/eq1_en sdi/eq0_en vee_cp vcc_cp lf+ cp_cap gnd cs/eq3_en vee_ddo0 vcc_ddo0 ddo0 de0_en gnd_drv vee_ddo1 vcc_ddo1 ddo1/rco de1_en ddi_sel0 ddi_sel1 bypass autobypass vcc_vco vee_vco ss0 ss1 vdd_1p8 locked los vdd_dig vss_dig gnd ddo0 auto/man ddo1/rco data/clock data_mute ddo1_disable sd/hd n/c n/c n/c n/c n/c
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 7 of 45 proprietary & confidential 1.2 pin descriptions table 1-1: GS2985 pin descriptions pin number name type description 1, 3 ddi0, ddi0 input serial digital differential input 0. 2 hif logic input host interface selection pin. active-low input. see section 4.15.14 . 4, 8, 12, 16, 32, 49 gnd power connect to gnd. 5, 7 ddi1, ddi1 input serial digital differential input 1. 6, 10, 24, 50, 54, 59, 64 n/c no connect do not connect. 9, 11 ddi2, ddi2 input serial digital differential input 2. 13, 15 ddi3, ddi3 input serial digital differential input 3. 14 rsvd reserved reserved pin. do not connect to this pin. 17, 18 ddi_sel[0:1] logic input selects one of four serial digital input signals for processing. see section 4.4 . 19 bypass logic input bypasses the reclocker stage. see section 4.12 . 20 autobypass logic input when high, this pin automatically bypasses the reclocker stage when the pll is not locked to a supported rate. see section 4.12 . 21 auto/ man logic input when set high, the standard is automatically detected from the input data rate. 22 vcc_vco power most positive power supply connection for the internal vco section. connect to a 3.3v supply with a 422 resistor, or to a 2.5v supply with a 267 resistor. 23 vee_vco power most negative power supply connection for the internal vco section. connect to gnd. 25, 26 ss0, ss1 bi-directional when auto/ man is high, ss[1:0] are outputs displaying the data rate to which the pll has locked to. when auto/ man is low, ss[1:0] are inputs forcing the pll to lock only to the selected data rate. see table 4-8 from section 4.10 . 27 vdd_1p8 power external capacitor for internal 1.8v digital supply. 28 locked output lock detect status signal. high when the pll is locked. 29 los output loss of signal status. high when the input signal is invalid. 30 vdd_dig power most positive power supply connection for the digital core. connect to 3.3v or 2.5v. 31 vss_dig power most negative power supply for the digital core. connect to gnd.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 8 of 45 proprietary & confidential 33 sd/ hd output this signal will be low for all rates other than 270mb/s. this signal is high for 270mb/s. 34 kbb analog input controls the loop bandwidth of the pll. leave this pin floating for serial reclocking applications. 35 ddo1_disable logic input disables the ddo1/rco and ddo1/ rco outputs when low. see section 4.14 . 36 data_mute logic input mutes the ddo0/ ddo0 and ddo1/ ddo1 (if data is selected) outputs when low. set high for normal operation. 37 data/ clock logic input data/ clock select. see section 4.14 . 38, 40 ddo1/rco, ddo1/rco output differential serial clock or data outputs. 39 de1_en logic input de-emphasis on/off pin for serial digital output 1. high = de-emphasis on low = de-emphasis off 41 vcc_ddo1 power most positive power supply connection for the ddo1/ ddo1 output driver. connect to 3.3v or 2.5v. 42 vee_ddo1 power most negative power supply connection for the ddo1/ ddo1 output driver. connect to gnd. 43 gnd_drv power connect to gnd. 44, 46 ddo0, ddo0 output differential serial digital outputs. 45 de0_en logic input de-emphasis on/off pin for serial digital output 0. high = de-emphasis on low = de-emphasis off 47 vcc_ddo0 power most positive power supply connection for the ddo0/ ddo0 output driver. connect to 3.3v or 2.5v. 48 vee_ddo0 power most negative power supply connection for the ddo0/ ddo0 output driver. connect to gnd. 51 xtal_buf_out output buffered output of the reference oscillator. 52 xtal+ output reference crystal output. 53 xtal- input reference crystal input. 55 cs/eq3_en input/logic input in host mode ( hif set low): chip select input for spi serial host interface. active-low input. in non-host mode ( hif set high): trace equalization on/off pin for serial digital differential input 3. active-high input. table 1-1: GS2985 pin descriptions pin number name type description
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 9 of 45 proprietary & confidential 56 sck/eq2_en input/logic input in host mode ( hif set low): burst-mode clock input for spi serial host interface. in non-host mode ( hif set high): trace equalization on/off pin for serial digital differential input 2. active-high input. 57 sdo/eq1_en input/logic input in host mode ( hif set low): serial digital data output for spi serial host interface. active-high output. in non-host mode ( hif set high): trace equalization on/off pin for serial digital differential input 1. active-high input. 58 sdi/eq0_en input/logic input in host mode ( hif set low): serial digital data input for spi serial host interface. active-high input. in non-host mode ( hif set high): trace equalization on/off pin for serial digital differential input 0. active-high input. 60 vee_cp power most negative power supply connection for the internal charge pump. connect to gnd. 61 vcc_cp power most positive power supply connection for the internal charge pump. connect to 3.3v or 2.5v 62 lf+ passive loop filter capacitor connection. (clf = 47nf). connect as shown in typical application circuit on page 41 . 63 cp_cap power external capacitor for internal ldo regulator supplying the charge pump circuit. ? center pad ? ground pad on bottom of package. connect to gnd. table 1-1: GS2985 pin descriptions pin number name type description
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 10 of 45 proprietary & confidential 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value supply voltage -0.5 to +3.6v dc input esd voltage 4kv storage temperature range -50oc < t a < 125oc operating temperature range -40oc to 85oc input voltage range -0.3 to (vcc + 0.3) v dc solder reflow temperature 260oc table 2-1: dc electrical characteristics parameter symbol conditions min ty p max units supply voltage vdd 3.3v 3.135 3.3 3.465 v 2.5v 2.375 2.5 2.625 v power (ddo1/rco disabled, minimum output swing) p vdd = 3.3v ? 250 325 mw vdd = 2.5v ? 180 235 mw power (ddo1/rco enabled, minimum output swing) vdd = 3.3v ? 290 390 mw vdd = 2.5v ? 210 275 mw power in power-down mode vdd = 3.3v ? 48 60 mw vdd = 2.5v ? 30 40 mw serial input termination ? differential 80 100 120 serial output termination ? differential 80 100 120 serial input common mode voltage ?? 1.6 ? vdd v serial output common mode voltage ?? ? vcc- ( vod /2) ? v vil (2.5v operation) ? vout vol, max -0.3 ? 0.7 v vil (3.3v operation) vout vol, max -0.3 ? 0.8 v
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 11 of 45 proprietary & confidential 2.3 ac electrical characteristics vih (2.5v operation) ? vout voh, min 1.7 ? vdd +0.3 v vih (3.3v operation) vout voh, min 2 ? vdd +0.3 v iin ? vin = 0v or vin = vdd ? +/-10 +/-20 a vol (2.5v operation) ? vdd = min, iol = 100 a ?? 0.4 v vol (3.3v operation) vdd = min, iol = 100 a ?? 0.4 v voh (2.5v operation) ? vdd = min, ioh = -100 a 2.1 ?? v voh (3.3v operation) vdd = min, ioh = -100 a vdd -0.4 ?? v hysteresis voltage (spi inputs) ? 2.5v operation ? 350 ? mv 3.3v operation ? 420 ? mv table 2-1: dc electrical characteristics (continued) parameter symbol conditions min ty p max units table 2-2: ac electrical characteristics parameter symbol conditions min ty p max units notes serial input data rate (for reclocking) dr sdo ? 0.27 ? 2.97 gb/s ? serial input data rate (bypass) ? dc ? 2.97 gb/s ? spi operating speed ?? ?? 10 mhz ? input voltage swing vsdi set atten_en = 1 for vsdi>1v pp 100 2000 mv p-pd ? output voltage swing vod default 300 400 500 mv p-pd ? see driver_1 register (0x01) addresses 8 & 9 in 4.15.14 host register map . 600 800 1000 mv p-pd ? input trace equalization ? low recommended setting for 0 to 10 inches of fr4 ? med recommended setting for 10 to 20 inches of fr4 ? high recommended setting for >20 inches of fr4 ?
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 12 of 45 proprietary & confidential output de-emphasis ? off - 0 ? 0 ? db ? on - 0 ? 0 ? db ? on - 1 ? 0.7 ? db ? on - 2 ? 1.3 ? db ? on - 3 ? 2 ? db ? on - 4 ? 2.6 ? db ? on - 5 ? 3.3 ? db ? on - 6 ? 4 ? db ? on - 7 ? 4.7 ? db ? input jitter tolerance square-wave modulated jitter 0.8 ?? ui ? loop bandwidth bw loop (270mb/s) kbb = vcc ? 170 ? khz ? kbb = float ? 340 ? khz ? kbb = gnd ? 680 ? khz ? bw loop (1485mb/s) kbb = vcc ? 0.875 ? mhz ? kbb = float ? 1.75 ? mhz ? kbb = gnd ? 3.5 ? mhz ? bw loop (2970mb/s) kbb = vcc ? 1.75 ? mhz ? kbb = float ? 3.5 ? mhz ? kbb = gnd ? 7.0 ? mhz ? pll lock time (asynchronous) t alock ?? 0.5 1 ms ? pll lock time (synchronous) t slock clf = 47nf, sd/ hd = 0 ? 0.5 4 s ? clf = 47nf, sd/ hd = 1 ? 510 s ? serial data output jitter intrinsic (ddo0) t oj(270mb/s) kbb = float prn 2^23-1 test pattern ? 0.01 0.02 ui 1 t oj(1485mb/s) kbb = float prn 2^23-1 test pattern ? 0.03 0.04 ui 1 t oj(2970mb/s) kbb = float prn 2^23-1 test pattern ? 0.05 0.08 ui 1 output rise/fall time tr/f 20% to 80% (400mv swing) ? 65 90 ps ? 20% to 80% (800mv swing) ? 80 110 ps ? output rise/fall time mismatch ?? ?? 15 ps ? table 2-2: ac electrical characteristics (continued) parameter symbol conditions min ty p max units notes
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 13 of 45 proprietary & confidential eye cross shift ? percentage of signal amplitude ?? 5% ? power supply noise rejection ? 50 - 100hz ? 100 ? mv p-p ? 100hz - 10mhz ? 40 ? mv p-p ? 10mhz - 1.485ghz ? 10 ? mv p-p ? notes: 1. accumulated jitter measured peak to peak differential over 1000 hits. table 2-2: ac electrical characteristics (continued) parameter symbol conditions min ty p max units notes
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 14 of 45 proprietary & confidential 3. input/output circuits figure 3-1: high-speed inputs (ddi0, ddi0 , ddi1, ddi1 , ddi2, ddi2 , ddi3, ddi3 ) figure 3-2: low-speed input with weak internal pull-up ( hif , rsvd, auto/ man , ddo1_disable , data_mute ) ddi ddi 25 25 25 25 5.55k 12.96k vcc vcc vcc in vref 1.4k vcc vcc 2.5a
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 15 of 45 proprietary & confidential figure 3-3: low-speed input with weak internal pull-down (ddi_sel0, ddi_sel1, bypass, autobypass, de1_en, de0_en) figure 3-4: data rate control/indicators (ss0, ss1) figure 3-5: low-speed outputs (locked, los, hd/ sd ) in vref 1.4k vcc vcc 2.5a vref 1.4k vcc vcc vcc ss0/ss1 tgate auto/man vcc ss0/ss1 vcc out vcc 972
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 16 of 45 proprietary & confidential figure 3-6: high-speed outputs ( ddo1 / rco , ddo1/rco, ddo0 , ddo0) figure 3-7: loop bandwidth control (kbb) ddo vcc 50 50 vcc vcc ddo kbb 1.4k vcc vref 1 vcc vref 2 vcc vcc
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 17 of 45 proprietary & confidential figure 3-8: crystal buffered output (xtal_buf_out) figure 3-9: high-speed crystal oscillator i/o (xtal-, xtal+) figure 3-10: spi inputs/eq ctrl ( cs /eq3_en, sck/eq2_en, sdi/eq0_en) vcc xtal_buff_out vcc vcc vcc xtal- vcc en en vcc xtal+ 246 in 1k vcc vcc 2.5a
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 18 of 45 proprietary & confidential figure 3-11: spi output/eq control (sdo/eq1_en) sdo vref 1.4k vcc vcc vcc 2.5a tgate spi sdo tri-state logic
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 19 of 45 proprietary & confidential 4. detailed description the GS2985 is a multi-standard reclocker for serial digital sdtv signals operating at 270mb/s, and hdtv signals operating at 1.485gb/s, 1.485/1.001gb/s, 2.97gb/s and 2.97/1.001gb/s. 4.1 serial data input the GS2985 features four differential input buffers. the serial data input signal is connected to the ddi0/ ddi0, ddi1/ ddi1, ddi2/ ddi2 and ddi3/ ddi3 input pins of the device. input signals can be single-ended or differential, dc or ac-coupled. the input circuit is self-biasing, to allow for simple ac or dc-coupling of input signals to the device. the serial digital data inputs are also compatible when dc-coupled with lvpecl or cml differential outputs from crosspoint switches which operate from 3.3v or 2.5v supplies. this includes but is not limited to: gs2974a, gs2974b, and gs2984 equalizers. 4.2 modes of operation the GS2985 has two modes of operation: legacy mode ( hif = high) and spi mode ( hif = low). in legacy mode, chip functions are controlled via pins only, and offers limited control of input equalization and output de-emphasis. in spi mode, access is gained to additional eq and de settings as well as access to additional features such as los adjustment, polarity invert, auto-mute, etc. 4.3 input trace equalization the GS2985 features adjustable trace equalization to compensate for pcb trace dielectric losses at 1.5ghz. the trace equalization has three peak-gain settings. the maximum peak gain value is optimized for compensating the high-frequency losses associated with 25 inches of 5-mil stripline in fr4 material. for boards with different striplines or materials, users can experiment to find the eq setting which optimizes their system performance. these settings are accessible via the serial host interface. each serial digital input; ddi, ddi includes a pin eqn_en to turn its trace equalizer on or off. when a pin eqn_en is tied low or left unconnected, the trace equalization for input n is set to the low range. when an eqn_en pin is tied high, and input n is selected, the trace equalization for input n is set to the medium range.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 20 of 45 proprietary & confidential the default peak-gain setting upon power-up is optimized for compensating the high-frequency losses associated with approximately 10 inches of 5-mil stripline in fr4 material. the eqn_en pins are multiplexed with the serial host interface pins. the eqn_en functionality is enabled when pin hif is tied high, as shown in table 4-2 : 4.4 4:1 input mux the GS2985 incorporates a 4:1 input mux, which allows the connection of four independent streams of video/data. there are four differential inputs (ddi[3:0] / ddi[3:0]). the active channel can be selected via the ddi_sel[1:0] pins as shown in table 4-3 . the ddi_sel pins include internal pull-downs, which pull the input voltage low if either pin is unconnected. active circuitry associated with the input buffers and trace eq can only be turned on for the selected input. inputs which are not selected have their input buffers and trace eqs turned off to save power. unused inputs can be either left floating, or tied to vcc. table 4-1: input trace equalization operation eqn_en setting trace equalization range low low high medium table 4-2: eqn_en pins multiplexed pin function sdi/eq0_en active-high logic input to enable trace-equalization for high-speed input channel 0. sdo/eq1_en active-high logic input to enable trace-equalization for high-speed input channel 1. sck/eq2_en active-high logic input to enable trace-equalization for high-speed input channel 2. cs/eq3_en active-high logic input to enable trace-equalization for high-speed input channel 3. table 4-3: input selection table ddi_sel[1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 21 of 45 proprietary & confidential 4.5 crystal buffer the GS2985 features a crystal buffer supporting a gennum recommended external 27mhz crystal. the GS2985 requires an external 27mhz reference clock for correct operation. this reference clock is generated by connecting a crystal to the xtal- and xtal+ pins of the device. alternately, a 27mhz external clock source can be connected to the xtal- pin of the device, while the xtal+ pin should be left floating. 4.6 los (loss of signal) detection the los (loss of signal) status pin is an active-high output that indicates when the serial digital input signal selected at the 4:1 input mux is invalid. in order for this output to be asserted, transitions must not be present for a period of t la = 5 - 10 s. after this output has been asserted, los will de-assert within t ld = 0 - 5 s after the appearance of a transition at the ddix input. see figure 4-1 . this signal is high (signal lost), when the number of data edges within a window is below a defined threshold. the output is automatically muted when los is detected. this signal is low (signal valid), when the number of data edges within a window is above a defined threshold. see table 4-4 . the los function is operational for all operating modes of the device. figure 4-1: los signal timing the los detector has two major modes. in legacy mode, a simple edge-based detector is used to monitor the received signal at the output of the data slicer. since the incoming signal has undergone considerable gain by this point, the legacy detector can be more susceptible to false de-assertion of los for unused channels which experience significant cross-talk from adjacent active channels. table 4-4: los operation los signal high invalid low valid data los t la t ld
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 22 of 45 proprietary & confidential the new los detector uses a measure of both signal amplitude and duration to minimize false detection of the impulse like signals that are characteristic of cross-talk. in this mode, the signal is tapped off at the output of the equalizer stage, prior to the high gain buffers. the threshold setting within the detector can be adjusted to increase or decrease its sensitivity. gennum recommends using the least sensitive threshold level. this provides the most margin against false de-assertion of los. the los mode can be selected by using the host interface, in register top_1 (address 0x02). 4.7 serial digital reclocker the output of the equalizer is fed to the reclocker. the function of the reclocker is to re-time the input signal and to generate system clocks. the reclocker operates at three frequencies; 2.97gb/s, 1.485gb/s and 270mb/s, and provides a minimum input jitter tolerance of 0.8ui to square-wave-modulated jitter at these rates. when there is no serial input signal, the internal clock maintains a frequency close to the expected incoming data rate, by locking to the external reference crystal. 4.8 lock detection the lock detect block indicates, via the active-high locked signal, when the device has achieved lock to the incoming data stream. the lock logic within the GS2985 includes a system that monitors the frequency and the phase of the incoming data, as well as a monitor to detect harmonic lock. the locked output signal is also available via the host interface. table 4-5: suggested los threshold settings los detection method select los threshold adjust input signal amplitude >250mv 0x1 0x0 200mv to 250mv 0x1 0x1 150mv to 200mv 0x1 0x2 <150mv 0x1 or 0x0 0x3 table 4-6: lock operation lock signal status high locked low not locked
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 23 of 45 proprietary & confidential 4.8.1 lock detect and asynchronous lock the reference crystal is used to assist the pll in achieving a short lock time. the lock detection algorithm is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down. the asynchronous lock time is defined as the time it takes the device to lock when a video signal is first applied to the serial digital inputs, or when the digital video signal rate changes. the synchronous lock time is defined as the time it takes the device to lock to a signal which has been momentarily interrupted. 4.9 serial data output the GS2985 features two current-mode differential output drivers, each capable of driving a maximum of 800mv pp , differential, into an external 100 differential load. each of the GS2985's output buffers include two on-chip, 50 termination resistors. 4.9.1 output signal interface levels the serial digital outputs of the GS2985 are compatible when dc-coupled with all gennum serial digital interface products that feature a differential lvpecl or cml receiver designed for sdi applications and operate from 3.3v or 2.5v supplies. this includes but is not limited to: gs2978, gs2988, and gs2989 cable drivers. 4.9.2 adjustable output swing it is possible, via the host interface, to force the output swing to 400mv pp or 800mv pp differential, when the outputs are terminated with 50 loads. the default output swing upon power-up is 400mv pp differential. 4.9.3 output de-emphasis the GS2985 features adjustable output de-emphasis to compensate for pcb trace dielectric losses. the output de-emphasis has eight settings, evenly distributed from a minimum of 0db (output de-emphasis off) to a peak de-emphasis setting that is optimized for compensating the high-frequency losses associated with approximately 20 inches of 5-mil stripline in fr4 material. these settings are accessible via the serial host interface. the action of the de-emphasis settings is to attenuate the trailing edge of the output data waveform relative to the output swings set through the host interface. each serial digital output ddon, ddon includes a den_en pin to turn its output de-emphasis on or off. de-emphasis is also turned off when in bypass mode.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 24 of 45 proprietary & confidential when den_en is set low or left unconnected, the de-emphasis for output n is off. when hif is high, these de_en controls select between off and a setting that compensates for roughly five inches of trace. all other settings are available only via the host interface. when a den_en pin is tied high, the output de-emphasis for output n is on. the default de-emphasis setting upon power-up is 0db (off). note: changing the de-emphasis setting will vary both v1 & v2 (see figure 4-2 ). figure 4-2: de-emphasis waveform 4.10 automatic and manual data rate selection the GS2985 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. the auto/ man pin selects automatic data rate detection mode (auto mode) when high and manual data rate selection mode (manual mode) when low. in auto mode, the ss[1:0] bi-directional pins become outputs and the bit pattern indicates the data rate at which the pll is currently locked to (or previously locked to). the search algorithm table 4-7: output de-emphasis den_en pin status of output n high output de-emphasis on low output de-emphasis off v1 v2 -v1 -v2 tx signal after de-emphasis 11110000 pattern 268 269 270 271 272 273 274 275 ui volts -0.6 -0.4 -0.2 0 0.2 0.4 0.6 de-emphasis (db) =20 log (v1/v2)
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 25 of 45 proprietary & confidential cycles through the data rates and starts over if that data rate is not found (see figure 4-3 ). a ?search algorithm? cycles through the supported data rates until lock is achieved, as shown in figure 4-3 below. figure 4-3: GS2985 automatic mode search algorithm in manual mode, the ss[1:0] pins become inputs and the data rate can be programmed. in this mode, the search algorithm is disabled and the GS2985's pll will only lock to the data rate selected in accordance with table 4-8 . 4.11 sd/ hd indication the sd/ hd signal indicates the output data rate of the device and can be connected to the sd/ hd input pin of dual slew rate cable drivers such as the gs2988. when this signal is high, the data rate is 270mb/s. this signal is low for all other data rates. this signal is also low when the device is operating in bypass mode (auto-bypass and user-bypass). the sd/ hd signal is low when the device is not locked. power up 270mb/s 1485mb/s 2970mb/s *note: the search algorithm does not necessarily begin with 270mb/s. table 4-8: data rate indication/selection bit pattern ss[1:0] data rate (mb/s) 0 reserved 1 270 2 1485 or 1485/1.001 3 2970 or 2970/1.001
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 26 of 45 proprietary & confidential 4.12 bypass mode in bypass mode, the GS2985 passes the data at the inputs, directly to the output. there are two pins that control the bypass function: bypass and autobypass. the bypass pin is an active-high signal which forces the GS2985 into bypass mode for as long as the pin is asserted high. the autobypass pin is an active-high signal that places the GS2985 into bypass mode only when the pll has not locked to a data rate. note that if bypass is high, this will override the autobypass functionality. when the GS2985's pll is not locked and bypass = low and autobypass = low, the serial digital output ddo/ ddo will produce invalid data. the autobypass function will bypass unsupported (non-reclocked) smpte sdi signal rates without producing bit errors: 143mb/s, 177mb/s, 360mb/s, 540mb/s. 4.13 dvb-asi the GS2985 also reclocks dvb-asi signals at 270mb/s. in auto mode, the device will automatically lock to the incoming 270mb/s signal. in manual mode, the ss[1:0] bits must be set to 01 (270mb/s) to ensure proper operation. 4.14 output mute and data/clock output selection the data_mute pin is provided to allow muting of the serial digital data output. setting data_mute = low will force the serial digital outputs ddo/ ddo to mute (statically latch high) under all conditions and operating modes. the ddo1_disable pin is provided to allow the second data/clock output to be powered down. when ddo1_disable is set low, the serial digital clock outputs ddo1/rco and ddo1/rco are muted and the driver is powered-down. the data/ clock pin is provided to allow the second output to emit a copy of the reclocked serial data or the recovered clock. table 4-9: bypass modes bypass autobypass device operation high x bypass mode low high bypass mode if the pll has not locked to a data rate low low power-up default. normal operation, part always tries to lock to the incoming data stream.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 27 of 45 proprietary & confidential when the data/ clock pin is set high, the ddo1/rco pin will output a copy of the serial digital output. when the data/ clock pin is set low, the ddo1/rco pin will output a copy of the recovered clock signal. 4.15 host interface 4.15.1 introduction the GS2985 offers a serial peripheral interface (spi) to access advanced features and programmability. the polarity of the hif pin tells the GS2985 whether or not the host interface is active ( hif = 0) or in legacy mode ( hif = 1). using the host interface, it is possible to override the control pin settings, and such settings will persist until the device has been powered-down and/or reset. the host interface is capable of reading hard-wired pin configuration, pin override settings and the values of all status monitoring pins. there is an optional 3-state feature available in the control status registers (csr) that puts the spi sdo to high-impedance when it?s not being used (register: top_1, bit: 2). the maximum operating speed of the spi is 10mhz. 4.15.2 legacy mode & start-up in legacy mode, basic configuration of the device (including a subset of equalizer and de-emphasis settings) are available at the pin level. in this mode, register settings are automatically set to default so that the GS2985 is live at power-up. 4.15.3 host interface mode & start-up in host interface mode, the user gains access to control and status registers (csrs) that manage advanced features. in this mode, equalizer and de-emphasis settings are set through the csr. the spi control port is functional at start-up without the need for a separate, external reset signal. however, all internal registers must be set to their default state by issuing a required reset command via the spi. table 4-10: configuration of GS2985 output drivers and mute/disable pins data_mute ddo1_disable data/ clock ddo0 ddo1/rco 1 1 0 data clock 111datadata 0 1 0 mute clock 0 1 1 mute mute 1 0 x data power down 0 0 x mute power down
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 28 of 45 proprietary & confidential this is done by setting the rst bit low in the command word. this will guarantee the csr will not start up in a random state. a simple way to issue the required reset of the csr is to hold the slave device?s sdi input low for an entire 64 cycle write communication. details of the write operation are found in section 4.15.6 below. 4.15.4 clock & data timing the spi signals are serial data input (sdi), serial data output (sdo), active low chip select ( cs), and serial clock input (sck). the host interface operates in spi mode 0, i.e. the sdi input will latch data in on the rising edge of sck. the sdo data output will transition on falling edges of sck. data is transmitted or received on the spi port msb first lsb last. figure 4-4: data clock alignment 4.15.5 single device operation for applications with a single device or applications with multiple devices where daisy chaining is not desired, the chain position bits c[6:0] should always be set to 0. as a by-product of the daisy chaining feature, read and write operations experience a 32 sck cycle latency from sdi to sdo. for more details on daisy-chaining, refer to section 4.15.8 on page 32 . figure 4-5: 16-bit command format sck cs cycle # 1 2 3 4 5 6 7 8 sdo 1 2 3 4 5 6 7 8 z z 1 2 3 4 5 6 7 8 z z sdi rw a[4:0] rst 0 0 read/ write reset address c n [6:0] = `0000000? chain position
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 29 of 45 proprietary & confidential 4.15.6 write operation - single device a write operation consists of a 16 bit command word and a 16 bit data word, followed by 32 cycles with the slave sdi held high. when writing to a single non-daisy chained device, the following format should be used: figure 4-6: single device write 1. at power-up, the device should be reset by setting the reset bit low. a simple way to accomplish a reset is to hold the slave sdi line low for an entire 64 cycle communication. 2. for a write operation, the r/w bit should be set to 0. 3. the 2nd and 3rd bits are reserved and should be set to 0. 4. the reset bit should always be set high for a normal write operation. 5. refer to the register map for information on address and data bits. 6. the slave sdi line shall be held high for 32 cycles before de-asserting chip select bar. 4.15.7 read operation - single device for reading from a device the following format should be used: figure 4-7: single device read command? [15:0] data [15:0] mosi command [15:0] data high 32 cycles cs rw a[4:0] r 0 0 r/w reset address c[6:0] = 0 chain position 16 bit command data [15:0] command [15:0] data [15:0] miso mosi miso command [15:0] data [15:0] command? [15:0] data high 16 cycles cs rw a[4:0] r 0 0 r/w reset address c[6:0] = 0 chain position 16 bit command data high 16 cycles data high 16 cycles
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 30 of 45 proprietary & confidential 1. for a read operation, the r/w bit should be set to 1. 2. the 2nd and 3rd bits are reserved and should be set to 0. 3. the reset bit should always be set high for a normal read operation. 4. data out at the slave sdo will appear after holding the slave sdi line high for 32 cycles. 5. the 16 bit data is now available on the slave sdo line. detailed timing diagrams for write and read can be seen in figure 4-8 and figure 4-9 .
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 31 of 45 proprietary & confidential figure 4-8: spi write timing figure 4-9: spi read timing r/w 0 r c0 c1 c2 c3 c4 c5 c6 a0 a1 a2 a4 a3 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sck cs sdi 32 cycles delayed sdo t 0 t 3 t 1 t 2 r/w 0 0 c0 c1 c2 c3 c4 c5 c6 a0 a1 a2 a4 a3 d15 d14 d13 d12 d d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 t 8 t 6 0 r r/w 0 0 r c0 c1 c2 c3 c4 c5 c6 a0 a1 a2 a4 a3 sck cs sdi 32 cycles delayed sdo t 0 t 3 t 1 t 2 c0 c1 c2 c3 c4 c5 c6 d15 d14 d13 d12 d7 d8 d9 d11 d10 t 8 r/w 0 0 r a0 a1 a2 a4 a3 table 4-11: gspi time delay parameter symbol conditions min ty p max units cs_n low before host_clk rising edge t 0 50% levels 1.5 ?? ns host_clk period t 1 100 ?? ns host_clk duty cycle t 2 40 50 60 % input data setup time t 3 1.5 ?? ns output hold time (15pf load) t 6 1.5 ?? ns cs_n high after last host_clk rising edge t 7 75% of host_clk period ?? ns input data hold time t 8 1.5 ?? ns
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 32 of 45 proprietary & confidential 4.15.8 daisy chain operation for applications with multiple GS2985 devices, it is possible to daisy-chain up to 127 parts in serial. in this configuration, the first device sdi should be connected to the spi master sdo. the serial data output of each device is then connected to the serial data input of the following device, and so on. the last device's sdo connects to the master's sdi. connecting devices in serial reduces the number of i/o ports required by the master by removing the need for additional chip select lines. figure 4-10: daisy chained spi bus the position of each GS2985 device in the serial chain is referred to as its chain position, with 0 corresponding to the first device. the chain position in the spi command word is decoded by each slave to know which device the master is talking to. each GS2985 slave is designed to output a replica of what it receives at its input after a delay of 32 cycles. the chain position part of the command is decremented by one in the duplicated command word at the output. each device in the chain will only execute the issued command if it verifies that the current chain position is set to 0. figure 4-11: chain position decoding spi master sck sdo sdi cs spi slave sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs spi slave spi slave chain position 0 chain position 1 chain position 2 GS2985 sdi sdo chain position -1 a[4:0] chain position a[4:0] c[6:0]= n 32 cycles GS2985 sdi sdo chain position -2 32 cycles c[6:0]= n-1 c[6:0]= n-2 a[4:0]
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 33 of 45 proprietary & confidential 4.15.9 read & write operation - daisy chained devices in a serial daisy chain configuration, read and/or write operations can be performed to multiple devices in the chain via consecutive operations. figure 4-12 below shows a simple 3 device configuration. figure 4-12: three devices in daisy chain configuration 4.15.10 writing to all devices when writing to all devices in the chain, a write command and corresponding data is required for each device. when the devices are being configured in the same way, all of them will have the same command and data with the exception of the chain position bits. this example assumes a 3-device daisy chain. a command is issued to the last device in the chain first, although it is possible to talk to the devices in any order. figure 4-13: daisy chain write 1. the first command issued in time is the command for the last device in the chain (chain position = 2). when the first device receives this command it will recognize that the chain position is 2 and will not execute the command. it will duplicate the command and data word at its output and decrement the chain position by one. 2. consecutive commands are issued for each device in the chain as shown. GS2985 sdi sdo GS2985 sdi sdo GS2985 sdi sdo mosi c miso data [15:0] command0 [15:0] data [15:0] mosi command2 [15:0] data high 32 cycles chain position = 2 cs data [15:0] command1 [15:0] chain position = 1 chain position = 0 miso data [15:0] command0' [15:0]
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 34 of 45 proprietary & confidential 4.15.11 writing to a single device in the chain the following example shows how to write to a single device in a chain: figure 4-14: daisy chain write to a single device 1. the command is issued to chain position n. 2. 32xn cycles are required to shift the command through n devices. the device at chain position n executes the command. 3. 32 additional cycles are required to complete the communication. 4.15.12 reading from all devices to read from all devices in the chain, a read command is issued for each device consecutively. after each command, the data is held high for 16 cycles. once a device recognizes it is being talked to, it will output data from the register requested. clock needs to be applied to cycle the output data through all devices in the chain. figure 4-15: daisy chain read 1. read command is issued to the last device in the chain, followed by read commands to the lower chain positions. 2. clock is applied to cycle the output data through the chain. datan [15:0] mosi commandn [15:0] data high 32xn cycles data high 32 cycles chain position = n cs chain position = n (n = 0 for first device in chain) datan [15:0] commandn? [15:0] miso command 2 command 1 sdi sdo data high for 16 cycles command 0 data high for 16 cycles data high for 16 cycles (chain position = 0) data2 data0 data1 data held high for 32x3 cycles command2? command1? command0? sdi sdo (chain position = 1) (chain position = 2) cs cs
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 35 of 45 proprietary & confidential 3. command2? refers to the altered or decremented command2. 4.15.13 reading from a single device in the chain the following example shows how to read from a single device in a chain: figure 4-16: daisy chain read from a single device 1. read command and 16 cycles of data held high are issued to chain position n. 2. 32xn cycles are applied with data high to cycle the command through n devices in the chain (note: n is 0 for first device in chain). device n executes the command. 3. with k representing the total number of devices in the chain, 32x(k-n-1) cycles are applied to bring the return data through the rest of the chain. 4. 16 additional cycles are applied until the data from device n is available on the master sdi. mosi miso commandn [15:0] datan [15:0] commandn? [15:0] data high 16 cycles data high 32xn cycles data high 32x(k-n-1) cycles data high 16 cycles data high 16 cycles chain position = n cs chain position = n (n = 0 for first device in chain) chain length = k (k 1)
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 36 of 45 proprietary & confidential 4.15.14 host register map table 4-12: host register map register name register address bit position access function default value valid range comments eq_1 0x00 15:10 rw reserved. 9 rw input attenuation enable (atten_en) 0x0 0 or 1 enable for input signals above 1vpp differential 8 rw equalizer offset correction enable 0x1 0 or 1 recommend always on 7 rw equalizer gain setting for ddi3 0x0 0 or 1 see supplementary table below 6 rw equalizer gain setting for ddi2 0x0 0 or 1 see supplementary table below 5 rw equalizer gain setting for ddi1 0x00 0 or 1 see supplementary table below 4 rw equalizer gain setting for ddi0 0x00 0 or 1 see supplementary table below 3 rw equalizer enable for ddi3 0x00 0 or 1 see supplementary table below 2 rw equalizer enable for ddi2 0x00 0 or 1 see supplementary table below 1 rw equalizer enable for ddi1 0x00 0 or 1 see supplementary table below 0 rw equalizer enable for ddi0 0x00 0 or 1 see supplementary table below equalizer decode logic eq_en eq_gain eq setting recommended trace lengths 0 0 low 0 to 10 inches of fr4 0 1 low 0 to 10 inches of fr4 1 0 med 10 to 20 inches of fr4 1 1 high 20 or more inches of fr4
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 37 of 45 proprietary & confidential driver_1 0x01 15:10 rw unused 0x0 0 or 1 ? 9 rw amplitude control for ddo1 0x1 0 or 1 0 = 800mv swing 1 = 400mv swing 8 rw amplitude control for ddo0 0x1 0 or 1 0 = 800mv swing 1 = 400mv swing 7:5 rw de-emphasis boost amplitude control for ddo1 0x2 0x0 to 0x7 0x0 = lowest setting 0x7 = highest setting 4:2 rw de-emphasis boost amplitude control for ddo0 0x2 0x0 to 0x7 0x0 = lowest setting 0x7 = highest setting 1 rw de-emphasis enable for ddo1 0x0 0 or 1 ? 0 rw de-emphasis enable for ddo0 0x0 0 or 1 ? table 4-12: host register map (continued) register name register address bit position access function default value valid range comments
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 38 of 45 proprietary & confidential top_1 0x02 15:9 rw reserved. 8:7 rw los threshold adjust 0x0 0x0 to 0x3 0x0 = least sensitive 0x3 = most sensitive 6:5 rw los detection method select 0x0 0x0 to 0x2 0x0 = legacy edge detection method 0x1 = new signal strength detection method 0x2 = dual detection method: both must detect a signal present for los to be low 4 rw los mute enable 0x0 0 or 1 when enabled the output will automatically mute if loss of signal is high 3 rw power down 0x0 0 or 1 chip powers down when asserted 2 rw tri-state enable for spi output 0x0 0 or 1 when enabled the spi sdo will be high z when cs is not selected 1 rw crystal buffer disable 0x0 0 or 1 0 = enabled 1 = disabled 0 rw data polarity invert 0x0 0 or 1 0 = not inverted 1 = inverted 0x03 to 0x0b reserved. table 4-12: host register map (continued) register name register address bit position access function default value valid range comments
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 39 of 45 proprietary & confidential pin_or_1 0x0c 15:13 rw unused 0x0 0 or 1 ? 12 rw data/ clock 0x0 0 or 1 ? 11 rw ddo1_disable 0x0 0 or 1 ? 10 rw data_mute 0x0 0 or 1 ? 9:8 rw kbb 0x0 0x0, 0x2 or 0x3 equivalent settings: 0x0 = kbb to ground 0x2 = kbb floating 0x3 = kbb to vcc 7 rw ss1 0x0 0 or 1 ? 6 rw ss0 0x0 0 or 1 ? 5 rw auto/ man 0x0 0 or 1 ? 4 rw autobypass 0x0 0 or 1 ? 3 rw bypass 0x0 0 or 1 ? 2 rw ddi_sel1 0x0 0 or 1 ? 1 rw ddi_sel0 0x0 0 or 1 ? 0 rw pin override enable 0x0 0 or 1 when enabled input values will be taken from this register instead of package pins status_1 0x0d 15:4 ro reserved. ?? ? 3 ro sd/ hd ?? ? 2 ro locked ?? ? 1 ro ss1 ?? ? 0 ro ss0 ?? ? 0x0e to 0x11 reserved. table 4-12: host register map (continued) register name register address bit position access function default value valid range comments
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 40 of 45 proprietary & confidential 4.16 device power-up in host mode ( hif pin tied low), control & status registers (csrs) may start up in a random state. there is a bit in the command word rst which will reset the csr when set low. in non-host mode ( hif pin tied high), the hif pin is used to trigger an internal reset signal to place all registers in a deterministic, default state upon power-up. in either host mode or non-host mode, other internal state machines (e.g. offset correction and pll) automatically recover from any state at start-up with no reset required. it takes ~10 s for the device to lock after start-up. 4.17 standby the purpose of standby mode is to allow operating power to be reduced when the device's functionality is not required, and to have a rapid and simple transition to full operation when the device is required. in order to achieve this, the device can be powered-down by writing a ?1? to the ?power down? bit located in register address 0x02.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 41 of 45 proprietary & confidential 5. typical application circuit figure 5-1: GS2985 typical application circuit 10nf ddi0 1 hif 2 ddi0 3 gnd 4 ddi1 5 6 ddi1 7 gnd 8 ddi2 9 10 ddi2 11 gnd 12 ddi3 13 14 ddi3 15 gnd 16 ddi_sel0 17 ddi_sel1 18 bypass 19 autobypass 20 auto/man 21 vcc_vco 22 vee_vco 23 24 ss0 25 ss1 26 vdd_1p8 27 locked 28 los 29 vdd_dig 30 vss_dig 31 gnd 32 vee_ddo0 48 vcc_ddo0 47 ddo0 46 de0_en 45 ddo0 44 gnd_drv 43 vee_ddo1 42 vcc_ddo1 41 ddo1/rco 40 de1_en 39 ddo1/rco 38 data/clock 37 data_mute 36 ddo1_disable 35 kbb 34 sd/hd 33 n/c 64 cp_cap 63 lf+ 62 vcc_cp 61 vee_cp 60 59 sdi/eq0_en 58 sdo/eq1_en 57 sck/eq2_en 56 cs/eq3_en 55 54 xtal- 53 xtal+ 52 xtal_buf_out 51 50 gnd 49 GS2985 bypass vcc gnd autobypass 10nf 10nf 27mhz 47nf tbd tbd vcc gnd locked 220nf 10nf los gnd 1f 220nf ss0 gnd 10f ss1 gnd 10nf vcc gnd gnd gnd gnd gnd vcc gnd gnd gnd gnd hif data input 1 data input 0 data input 2 data input 3 sd/hd auto/man data/clock data_mute ddo1_disable data output 0 data output 1/ serial clock kbb n/c n/c n/c n/c rsvd n/c n/c ddi_sel0 ddi_sel1 sdi/eq0_en sdo/eq1_en sck/eq2_en cs/eq3_en xtal_buf_out 1m vcc r* note: r* value is set to 267 for 2.5v supply or 422 for 3.3v supply.
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 42 of 45 proprietary & confidential 6. package and ordering information 6.1 package dimensions
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 43 of 45 proprietary & confidential 6.2 recommended pcb footprint 6.3 packaging data note: all dimensions are in millimeters. 7.10 7.10 8.70 8.70 0.50 0.25 0.55 center pad parameter value package type 9mm x 9mm 64-pin qfn moisture sensitivity level (per jedec j-std-020c) 3 junction to case thermal resistance, j-c 9.1c/w junction to air thermal resistance, j-a (at zero airflow) 21.5c/w junction to board thermal resistance, j-b 5.6c/w psi, 0.2c/w pb-free and rohs compliant yes
GS2985 multi-rate sdi reclocker with equalization & de-emphasis data sheet 36663 - 5 july 2012 44 of 45 proprietary & confidential 6.4 marking diagram 6.5 solder reflow profile figure 6-1: maximum pb-free solder reflow profile 6.6 ordering information GS2985 xxxxe3 yyww pin 1 id 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part number package temperature range GS2985 GS2985-ine3 pb-free 64-pin qfn -40c to 85c GS2985 GS2985-inte3 pb-free 64-pin qfn (250pc. tape and reel) -40c to 85c GS2985 GS2985-inte3z pb-free 64-pin qfn (2.5k tape and reel) -40c to 85c
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